CDCE706PWR
Active300-MHZ, LVCMOS, PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
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CDCE706PWR
Active300-MHZ, LVCMOS, PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCE706PWR |
|---|---|
| Differential - Input:Output | Yes/No |
| Frequency - Max [Max] | 300 MHz |
| Input | LVCMOS, Crystal |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output [custom] | 1:6 |
| Supplier Device Package | 20-TSSOP |
| Type | Spread Spectrum Clock Driver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.55 | |
| 10 | $ 7.72 | |||
| 25 | $ 7.36 | |||
| 100 | $ 6.39 | |||
| 250 | $ 6.11 | |||
| 500 | $ 5.57 | |||
| 1000 | $ 4.85 | |||
| Digi-Reel® | 1 | $ 8.55 | ||
| 10 | $ 7.72 | |||
| 25 | $ 7.36 | |||
| 100 | $ 6.39 | |||
| 250 | $ 6.11 | |||
| 500 | $ 5.57 | |||
| 1000 | $ 4.85 | |||
| Tape & Reel (TR) | 2000 | $ 4.67 | ||
| Texas Instruments | LARGE T&R | 1 | $ 7.53 | |
| 100 | $ 6.14 | |||
| 250 | $ 4.82 | |||
| 1000 | $ 4.09 | |||
Description
General part information
CDCE706 Series
The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE706 is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency.
The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.
To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.
Documents
Technical documentation and resources
