Zenode.ai Logo
Beta
Log InSign Up
CDIP (J)
Integrated Circuits (ICs)

SN54196J

Active
Texas Instruments

50/30/100-MHZ PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES

Deep-Dive with AI

Search across all available documentation for this part.

Documents50/30/100-MHz Presettable Decade Or Binary Counters/Latches datasheet (Rev. A)
CDIP (J)
Integrated Circuits (ICs)

SN54196J

Active
Texas Instruments

50/30/100-MHZ PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES

Deep-Dive with AI

Documents50/30/100-MHz Presettable Decade Or Binary Counters/Latches datasheet (Rev. A)

Technical Specifications

Parameters and characteristics for this part

SpecificationSN54196J
Count Rate70 MHz
DirectionUp
Logic TypeCounter, Decade
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case14-CDIP
ResetAsynchronous
Supplier Device Package14-CDIP
Trigger TypeNegative Edge
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 24.21
100$ 21.14
250$ 16.30
1000$ 14.58

Description

General part information

SN54196 Series

These high-speed monolithic counters consist of four d-c coupled, master-slave flip-flops, which are internally interconnected to provide either a divide-by-two and a divide-by-five counter (’196, ’LS196, ’S196) or a divide-by-two and a divide-by-eight counter (’197, ’LS197, ’S197). These four counters are fully programmable; that is, the outputs may be preset to any state by placing a low on the count/load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independent of the state of the clocks.

During the count operation, transfer of information to the outputs occurs on the negative-going edge of the clock pulse. These counters feature a direct clear which when taken low sets all outputs low regardless of the states of the clocks.

These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged when the count/load is high and the clock inputs are inactive.