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24-SOIC
Integrated Circuits (ICs)

1523MLF

Obsolete
Renesas Electronics Corporation

VIDEO CLOCK SYNTHESIZER WITH I2C PROGRAMMABLE DELAY

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24-SOIC
Integrated Circuits (ICs)

1523MLF

Obsolete
Renesas Electronics Corporation

VIDEO CLOCK SYNTHESIZER WITH I2C PROGRAMMABLE DELAY

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

Specification1523MLF
Differential - Input:Output [x]False
Differential - Input:Output [y]True
Divider/MultiplierYes/No
Frequency - Max [Max]250 MHz
InputClock
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
OutputLVPECL, SSTL-3
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
PLLTrue
Ratio - Input:Output [custom]1:3
Supplier Device Package24-SOIC
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 0$ 0.00

Description

General part information

1523 Series

The 1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IDT's advanced low-voltage CMOS mixed-mode technology, the 1523 is an effective phase controlled clock synthesizer and also supports video projectors and displays at resolutions from VGA to beyond UXGA. The 1523 offers clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase Adjust (DPA) allows I2C™ control of the output clock's phase relative to the input sync signal. A second, half speed set of outputs that can be separately enabled allows such applications as clocking analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output, or the input HSYNC after being sharpened by the Schmitt trigger. Both signals are then delayed by the DPA. The advanced PLL uses either its internal programmable feedback divider or an external divider. Either the internal or external loop filters is software selectable. The COAST input pin disables the PLL's charge pump, causing the device to idle at the current speed for short periods of time, such as vertical blanking intervals. The device is programmed by a standard I2C-bus serial interface and is available in a 24-pin, wide small-outline integrated circuit (SOIC) package.

Documents

Technical documentation and resources