
MC100LVEL31DTR2G
ActiveFLIP FLOP D-MASTER-SLAVE TYPE POS-EDGE 1-ELEMENT 8-PIN TSSOP T/R

MC100LVEL31DTR2G
ActiveFLIP FLOP D-MASTER-SLAVE TYPE POS-EDGE 1-ELEMENT 8-PIN TSSOP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | MC100LVEL31DTR2G |
|---|---|
| Clock Frequency | 2.9 GHz |
| Current - Quiescent (Iq) | 35 mA |
| Function | Reset, Set(Preset) |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 8-MSOP, 8-TSSOP |
| Package / Case | 3 mm |
| Package / Case [custom] | 0.118 in |
| Supplier Device Package | 8-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | -3 V |
| Voltage - Supply [Min] | -3.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.16 | |
| 10 | $ 7.37 | |||
| 25 | $ 7.02 | |||
| 100 | $ 5.83 | |||
| 250 | $ 5.31 | |||
| 500 | $ 4.97 | |||
| 1000 | $ 4.45 | |||
| Digi-Reel® | 1 | $ 8.16 | ||
| 10 | $ 7.37 | |||
| 25 | $ 7.02 | |||
| 100 | $ 5.83 | |||
| 250 | $ 5.31 | |||
| 500 | $ 4.97 | |||
| 1000 | $ 4.45 | |||
| Tape & Reel (TR) | 2500 | $ 4.28 | ||
| Newark | Each (Supplied on Full Reel) | 1 | $ 5.33 | |
| 3000 | $ 5.09 | |||
| 6000 | $ 4.75 | |||
| 12000 | $ 4.41 | |||
| 18000 | $ 4.25 | |||
| 30000 | $ 4.18 | |||
Description
General part information
MC100LVEL31 Series
The MC100LVEL31 is a D flip-flop with set and reset. The device is functionally equivalent to the EL31 device but operates from a 3.3V supply. With propagation delays and output transition times essentially equivalent to the EL31, the LVEL31 is ideally suited for those applications which require the ultimate in AC performance at low power supply voltages.Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.
Documents
Technical documentation and resources