IS43QR16256B-083RBLI 256Mx16 DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight banks (2 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operations to the DDR4 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence.