CD74HC4520E
ActiveHIGH SPEED CMOS LOGIC DUAL BINARY UP-COUNTERS
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CD74HC4520E
ActiveHIGH SPEED CMOS LOGIC DUAL BINARY UP-COUNTERS
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC4520E |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up |
| Logic Type | Binary Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 0.3 in |
| Package / Case | 16-DIP |
| Package / Case | 7.62 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-PDIP |
| Timing | Synchronous |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.54 | |
| 10 | $ 0.48 | |||
| 25 | $ 0.45 | |||
| 100 | $ 0.36 | |||
| 250 | $ 0.34 | |||
| 500 | $ 0.29 | |||
| 1000 | $ 0.25 | |||
| 1024 | $ 0.29 | |||
| Texas Instruments | TUBE | 1 | $ 0.65 | |
| 100 | $ 0.44 | |||
| 250 | $ 0.34 | |||
| 1000 | $ 0.23 | |||
Description
General part information
CD74HC4520 Series
The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
Documents
Technical documentation and resources
