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54-WFQFN Exposed Pad
Integrated Circuits (ICs)

DS125BR820NJYR

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Texas Instruments

12-GBPS 8-CHANNEL LINEAR REDRIVER WITH EQUALIZATION

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54-WFQFN Exposed Pad
Integrated Circuits (ICs)

DS125BR820NJYR

Active
Texas Instruments

12-GBPS 8-CHANNEL LINEAR REDRIVER WITH EQUALIZATION

Technical Specifications

Parameters and characteristics for this part

SpecificationDS125BR820NJYR
ApplicationsPCIe, SATA, SAS
Current - Supply220 mA
Data Rate (Max)12.5 Gbps
Delay Time80 ps
InputCML
Mounting TypeSurface Mount
Number of Channels8
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputCML
Package / Case54-WFQFN Exposed Pad
Signal ConditioningInput Equalization, Output De-Emphasis
Supplier Device Package54-WQFN (10x5.5)
TypeReDriver, Buffer
Voltage - Supply [Max]3.3 V
Voltage - Supply [Min]2.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 15.87
Digi-Reel® 1$ 15.87
Tape & Reel (TR) 2000$ 9.67
Texas InstrumentsLARGE T&R 1$ 12.42
100$ 10.85
250$ 8.36
1000$ 7.48

Description

General part information

DS125BR820 Series

The DS125BR820 is an extremely low-power high-performance repeater/redriver designed to support eight channels carrying high speed interface up to 12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA, and PCIe. The receiver’s continuous time linear equalizer (CTLE) provides high frequency boost that is programmable from 3 to 10 dB at 6 GHz (12 Gbps) followed by a linear output driver. The CTLE receiver is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin axial-copper cables. The programmable equalization maximizes the flexibility of physical placement within the interconnect channel and improves overall channel performance.

When operating in 40G-CR4/KR4, SAS/SATA, and PCIe applications, the DS125BR820 preserves transmit signal characteristics, thereby allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency in the link training protocol facilitates system level interoperability and minimizes latency.

The programmable settings can be applied easily via pin control, software (SMBus or I2C), or direct loading from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver.