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32-TQFN_488AM
Integrated Circuits (ICs)

MC10EP451MNG

Obsolete
ON Semiconductor

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE/NEG-EDGE 1-ELEMENT 32-PIN QFN EP TUBE

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32-TQFN_488AM
Integrated Circuits (ICs)

MC10EP451MNG

Obsolete
ON Semiconductor

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE/NEG-EDGE 1-ELEMENT 32-PIN QFN EP TUBE

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationMC10EP451MNG
Clock Frequency3 GHz
Current - Quiescent (Iq)125 mA
Mounting TypeSurface Mount
Number of Bits per Element6
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case32-VFQFN Exposed Pad
Supplier Device Package32-QFN (5x5)
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]-5.5 V
Voltage - Supply [Min]-3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 19$ 16.61

Description

General part information

MC10EP451 Series

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE+ 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.

Documents

Technical documentation and resources