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144-FCBGA
Integrated Circuits (ICs)

ADC09QJ1300AAVTQ1

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Texas Instruments

AUTOMOTIVE QUAD-CHANNEL, 9-BIT, 1.3-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE

144-FCBGA
Integrated Circuits (ICs)

ADC09QJ1300AAVTQ1

Active
Texas Instruments

AUTOMOTIVE QUAD-CHANNEL, 9-BIT, 1.3-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE

Technical Specifications

Parameters and characteristics for this part

SpecificationADC09QJ1300AAVTQ1
ArchitecturePipelined, SAR
ConfigurationADC
Data InterfaceJESD204C, Serial
FeaturesInternal Oscillator
GradeAutomotive
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters4
Number of Bits9
Number of Inputs4
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / CaseFCBGA, 144-FBGA
QualificationAEC-Q100
Ratio - S/H:ADC0:1
Reference TypeSupply
Sampling Rate (Per Second)1.3 G
Supplier Device Package144-FCBGA (10x10)
Voltage - Supply, Analog [Max]2 V, 1.15 V
Voltage - Supply, Analog [Min]1.8 V, 1.05 V
Voltage - Supply, Digital [Max]1.15 V
Voltage - Supply, Digital [Min]1.05 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 250$ 70.77
Texas InstrumentsSMALL T&R 1$ 62.52
100$ 56.59
250$ 54.98
1000$ 53.90

Description

General part information

ADC09QJ1300-Q1 Series

ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.