
SN74ALVCH16646DGVR
Active16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
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SN74ALVCH16646DGVR
Active16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16646DGVR |
|---|---|
| Current - Output High, Low | 24 mA |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 3-State |
| Package / Case | 0.173 in |
| Package / Case | 56-TFSOP |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 56-TVSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.75 | |
| Digi-Reel® | 1 | $ 2.75 | ||
| Tape & Reel (TR) | 2000 | $ 1.26 | ||
| 6000 | $ 1.21 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.07 | |
| 100 | $ 1.71 | |||
| 250 | $ 1.23 | |||
| 1000 | $ 0.92 | |||
Description
General part information
SN74ALVCH16646 Series
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ALVCH16646.
Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data may be stored in one register and/or B data may be stored in the other register.
Documents
Technical documentation and resources