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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74LS85N

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Texas Instruments

LOGIC, 4BIT MAG COMPARATOR, 16DIP

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16-DIP SOT38-1
Integrated Circuits (ICs)

SN74LS85N

Active
Texas Instruments

LOGIC, 4BIT MAG COMPARATOR, 16DIP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LS85N
Current - Output High, Low [custom]400 µA
Current - Output High, Low [custom]8 mA
Max Propagation Delay @ V, Max CL45 ns
Mounting TypeThrough Hole
Number of Bits4
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
OutputActive High
Output FunctionA<B, A>B, A=B
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
TypeMagnitude Comparator
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.61
10$ 1.45
25$ 1.36
100$ 1.16
250$ 1.09
500$ 0.95
1000$ 0.79
2500$ 0.74
5000$ 0.71
Texas InstrumentsTUBE 1$ 1.47
100$ 1.13
250$ 0.83
1000$ 0.59

Description

General part information

SN74LS85 Series

These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.

These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.

Documents

Technical documentation and resources