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8-VSSOP
Integrated Circuits (ICs)

OPA2333AIDGKRG4

Unknown
Texas Instruments

1.8-V, 17-ΜA, TWO-CHANNEL, MICROPOWER ZERO-DRIFT CMOS OPERATIONAL AMPLIFIER

8-VSSOP
Integrated Circuits (ICs)

OPA2333AIDGKRG4

Unknown
Texas Instruments

1.8-V, 17-ΜA, TWO-CHANNEL, MICROPOWER ZERO-DRIFT CMOS OPERATIONAL AMPLIFIER

Technical Specifications

Parameters and characteristics for this part

SpecificationOPA2333AIDGKRG4
Amplifier TypeCMOS, Zero-Drift
Current - Input Bias70 pA
Current - Output / Channel5 mA
Current - Supply17 µA
Gain Bandwidth Product350 kHz
Mounting TypeSurface Mount
Number of Circuits2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeRail-to-Rail
Package / Case8-MSOP, 8-TSSOP
Package / Case3 mm
Package / Case [custom]0.118 in
Slew Rate0.16 V/µs
Voltage - Input Offset2 çV
Voltage - Supply Span (Max) [Max]5.5 V
Voltage - Supply Span (Min) [Min]1.8 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2500$ 1.95
5000$ 1.88
Texas InstrumentsLARGE T&R 1$ 2.53
100$ 2.21
250$ 1.55
1000$ 1.25

Description

General part information

OPA2333A-EP Series

The OPA2333P is a CMOS operational amplifier that uses a proprietary auto-calibration technique to simultaneously provide very low offset voltage (10 µV, maximum) and near-zero drift over time and temperature. This miniature, high-precision, low quiescent current amplifier offers high-impedance inputs that have a common-mode range 100 mV beyond the rails, and rail-to-rail output that swings within 50 mV of the rails. Single or dual supplies as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V) can be used. This device is optimized for low-voltage, single-supply operation.

The OPA2333P also features a specified maximum start-up time. Specified start-up time ensures high-precision performance after 500 µs of powering the amplifier, allowing for reliable use in dynamic supply operation.

The OPA2333P offers excellent CMRR without the crossover associated with traditional complementary input stages. This design results in superior performance for driving analog-to-digital converters (ADCs) without degradation of differential linearity.