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VSON (DRB)
Integrated Circuits (ICs)

TPS3431SDRBR

Active
Texas Instruments

STANDARD PROGRAMMABLE WATCHDOG TIMER WITH ENABLE

VSON (DRB)
Integrated Circuits (ICs)

TPS3431SDRBR

Active
Texas Instruments

STANDARD PROGRAMMABLE WATCHDOG TIMER WITH ENABLE

Technical Specifications

Parameters and characteristics for this part

SpecificationTPS3431SDRBR
Current - Supply10 µA
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case8-VDFN Exposed Pad
Supplier Device Package8-SON (3x3)
TypeWatchdog Circuit
Voltage - Supply [Max]6.5 V
Voltage - Supply [Min]1.8 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.71
10$ 1.54
25$ 1.45
100$ 1.24
250$ 1.16
500$ 1.02
1000$ 0.84
Digi-Reel® 1$ 1.71
10$ 1.54
25$ 1.45
100$ 1.24
250$ 1.16
500$ 1.02
1000$ 0.84
Tape & Reel (TR) 3000$ 0.78
6000$ 0.75
Texas InstrumentsLARGE T&R 1$ 1.29
100$ 1.06
250$ 0.76
1000$ 0.57

Description

General part information

TPS3431 Series

The TPS3431 is a standard programmable watchdog timer with an enable feature for a wide variety of applications. The watchdog timeout features a 15% accuracy, high-precision timing (–40°C to +125°C) and 2.5% typical at 25°C. The watchdog timeout can be programmed either by an external capacitor, or by factory-programmed default delay settings. The watchdog can be disabled via the Enable pin or the SET logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3431 is available in a small 3.00-mm × 3.00-mm, 8-pin VSON package.

The TPS3431 is a standard programmable watchdog timer with an enable feature for a wide variety of applications. The watchdog timeout features a 15% accuracy, high-precision timing (–40°C to +125°C) and 2.5% typical at 25°C. The watchdog timeout can be programmed either by an external capacitor, or by factory-programmed default delay settings. The watchdog can be disabled via the Enable pin or the SET logic pins to avoid undesired watchdog timeouts during the development process.