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20-SOIC
Integrated Circuits (ICs)

CD74HC299M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC 8-BIT UNIVERSAL SHIFT REGISTER WITH 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Implications of Slow or Floating CMOS Inputs (Rev. E)+13
20-SOIC
Integrated Circuits (ICs)

CD74HC299M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC 8-BIT UNIVERSAL SHIFT REGISTER WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Implications of Slow or Floating CMOS Inputs (Rev. E)+13

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HC299M
FunctionUniversal
Logic TypeMultiplexed, Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 1.23
100$ 0.95
250$ 0.70
1000$ 0.50

Description

General part information

CD74HC299 Series

The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0– I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition.

The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three-state input/output I(/O) port has three modes of operation: