SN75ALS162DWR
ActiveOCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
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SN75ALS162DWR
ActiveOCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN75ALS162DWR |
|---|---|
| Duplex | Half |
| Mounting Type | Surface Mount |
| Number of Drivers/Receivers [custom] | 8 |
| Number of Drivers/Receivers [custom] | 8 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 24-SOIC |
| Package / Case [custom] | 7.5 mm |
| Package / Case [custom] | 0.295 in |
| Protocol | IEEE 488 |
| Receiver Hysteresis | 650 mV |
| Supplier Device Package | 24-SOIC |
| Type | Transceiver |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.71 | |
| 10 | $ 6.00 | |||
| 25 | $ 5.30 | |||
| 100 | $ 4.52 | |||
| 250 | $ 4.14 | |||
| 500 | $ 3.91 | |||
| 1000 | $ 3.72 | |||
| Digi-Reel® | 1 | $ 8.71 | ||
| 10 | $ 6.00 | |||
| 25 | $ 5.30 | |||
| 100 | $ 4.52 | |||
| 250 | $ 4.14 | |||
| 500 | $ 3.91 | |||
| 1000 | $ 3.72 | |||
| Tape & Reel (TR) | 2000 | $ 3.77 | ||
| Texas Instruments | LARGE T&R | 1 | $ 5.80 | |
| 100 | $ 4.72 | |||
| 250 | $ 3.71 | |||
| 1000 | $ 3.15 | |||
Description
General part information
SN75ALS162 Series
The SN75ALS162 eight-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed, advanced low-power Schottky process device designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS162 provides the complete 16-wire interface for the IEEE 488 bus.
The SN75ALS162 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SC input allows the REN and IFC transceivers to be controlled independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when VCC= 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled.
Documents
Technical documentation and resources