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SOIC (D)
Integrated Circuits (ICs)

CD74HC139M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

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SOIC (D)
Integrated Circuits (ICs)

CD74HC139M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HC139M
Circuit1 x 2:4
Current - Output High, Low [custom]5.2 mA
Current - Output High, Low [custom]5.2 mA
Independent Circuits2
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
TypeDecoder/Demultiplexer
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.43
Texas InstrumentsTUBE 1$ 1.23
100$ 0.83
250$ 0.64
1000$ 0.43

Description

General part information

SN74HC139-Q1 Series

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enableGinput can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.