Specification	DRA777PSIGACDQ1

Additional Interfaces	McSPI, CANbus, PCIe, McASP, QSPI, MMC/SD/SDIO, IrDA, I2C, TDM, DMA, UART, I2S
Co-Processors/DSP	C66x, ARM® Cortex®-M4, IVA
Core Processor	ARM® Cortex®-A15
Display & Interface Controllers	DVI, LCD, HDMI
Ethernet	1 Gbps
Grade	Automotive
Graphics Acceleration	True
Mounting Type	Surface Mount
Number of Cores/Bus Width [custom]	32 Bit
Number of Cores/Bus Width [custom]	2
Operating Temperature [Max]	125 ¯C
Operating Temperature [Min]	-40 °C
Package / Case	FCBGA, 784-LFBGA
Qualification	AEC-Q100
RAM Controllers	DDR2, DDR3L, DDR3
SATA	3 Gbps
Security Features	Cryptography, Secure Debug, Secure Storage, Software IP Protection, Isolation Firewalls, Device Identity, Boot Security
Speed	1.8 GHz
USB	USB 2.0 (3), USB 3.0 (1)
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1.8 V

DRA77P Series

High performance multi-core SoCs with extended peripherals and ISP for digital cockpit applications

Part	Package / Case	Additional Interfaces	Ethernet	Graphics Acceleration	Voltage - I/O	Qualification	Grade	Number of Cores/Bus Width [custom]	Number of Cores/Bus Width [custom]	Security Features	SATA	RAM Controllers	Speed	Operating Temperature [Min]	Operating Temperature [Max]	Display & Interface Controllers	Core Processor	Co-Processors/DSP	Mounting Type	USB
Texas Instruments DRA777PSIGACDQ1	784-LFBGA FCBGA	CANbus DMA I2C I2S IrDA McASP McSPI MMC/SD/SDIO PCIe QSPI TDM UART	1 Gbps		1.35 V 1.5 V 1.8 V 3.3 V	AEC-Q100	Automotive	32 Bit	2	Boot Security Cryptography Device Identity Isolation Firewalls Secure Debug Secure Storage Software IP Protection	3 Gbps	DDR2 DDR3 DDR3L	1.8 GHz	-40 °C	125 ¯C	DVI HDMI LCD	ARM® Cortex®-A15	ARM® Cortex®-M4 C66x IVA	Surface Mount	USB 2.0 (3) USB 3.0 (1)

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

DRA77P Series

DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Documents

Technical documentation and resources

DRA777PSIGACDQ1

Deep-Dive with AI

DRA777PSIGACDQ1

Deep-Dive with AI

Technical Specifications

DRA77P Series

Pricing

Description

DRA77P Series

Documents

ECC/EDC on TDAxx (Rev. B)

Android Boot Optimization on DRA7xx Devices (Rev. A)

The Implementation of YUV422 Output for SRV

Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)

Jacinto6 Spread Spectrum Clocking Configuration (Rev. A)

Jacinto6 Android Video Decoder Software Design Specification User's Guide

Early Splash Screen on DRA7x Devices

MMC DLL Tuning (Rev. B)

Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B)

Flashing Utility - mflash

Integrating AUTOSAR on TI SoC: Fundamentals

DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D)

DRA74x_75x/DRA72x Performance (Rev. A)

Informational ADAS as Software Upgrade to Today’s Infotainment Systems

Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices

Tools and Techniques for Audio Debugging

Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC

Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices

Flashing Binaries to DRA7xx Factory Boards Using DFU

Integrating New Cameras With Video Input Port on DRA7xx SoCs

Gstreamer Migration Guidelines

Linux Boot Time Optimizations on DRA7xx Devices

Achieving Early CAN Response on DRA7xx Devices

Robust Rear-View Camera (RVC) App Report

DRA77xP, DRA76xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. E)

Tools and Techniques to Root Case Failures in Video Capture Subsystem

Building your application with security in mind (Rev. E)

Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)

DRA7xx Silicon Errata (Rev. B)

Sharing VPE Between VISIONSDK and PSDKLA

Revolutionize the automotive cockpit

Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A)

Optimization of GPU-Based Surround View on TI’s TDA2x SoC

IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC

A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B)

Today’s high-end infotainment soon becoming mainstream

Debugging Tools and Techniques With IPC3.x

Jacinto6 Android Video Encoder Software Design Specification User's Guide

Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices

Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)

Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device

AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E)

DRA77P Series