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Technical Specifications
Parameters and characteristics for this part
| Specification | TMS5703137BPGEQQ1 |
|---|---|
| Connectivity | SPI, Ethernet, LINbus, I2C, FlexRay, CANbus, UART/USART, MibSPI, EBI/EMI, SCI |
| Core Processor | ARM® Cortex®-R4F |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 12 |
| Data Converters [custom] | 24 |
| EEPROM Size | 64 K |
| Grade | Automotive |
| Mounting Type | Surface Mount |
| Number of I/O | 58 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External |
| Package / Case | 144-LQFP |
| Peripherals | WDT, DMA, PWM, POR |
| Program Memory Size | 3 MB |
| Program Memory Type | FLASH |
| Qualification | AEC-Q100 |
| RAM Size | 256 K |
| Speed | 160 MHz |
| Supplier Device Package | 144-LQFP (20x20) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
TMS570LS3137-EP Series
The TMS570LS31x5/21x5 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The TMS570LS31x5/21x5 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.
The TMS570LS3135 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2135 device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2125 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.
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