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CDIP (J)
Integrated Circuits (ICs)

CD4060BF

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Texas Instruments

CMOS 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER AND OSCILLATOR

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CDIP (J)
Integrated Circuits (ICs)

CD4060BF

Active
Texas Instruments

CMOS 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER AND OSCILLATOR

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4060BF
Count Rate24 MHz
DirectionUp
Logic TypeBinary Counter
Mounting TypeThrough Hole
Number of Bits per Element [custom]14
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case7.62 mm, 0.3 in
Package / Case16-CDIP
ResetAsynchronous
Supplier Device Package16-CDIP
Trigger TypeNegative Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 14.07
100$ 12.29
250$ 9.48
1000$ 8.48

Description

General part information

CD4060B-MIL Series

CD4060B consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A RESET input is provided which resets the counter to the all-O's state and disables the oscillator. A high level on the RESET line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are fully buffered. Schmitt trigger action on the input-pulse line permits unlimited input-pulse rise and fall times.

The CD4060B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4060B consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A RESET input is provided which resets the counter to the all-O's state and disables the oscillator. A high level on the RESET line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are fully buffered. Schmitt trigger action on the input-pulse line permits unlimited input-pulse rise and fall times.

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