Specification	SN74AS194D

Function	Universal
Logic Type	Register, Bidirectional
Mounting Type	Surface Mount
Number of Bits per Element	4
Number of Elements	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Push-Pull
Package / Case	16-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Supplier Device Package	16-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74AS194 Series

4-Bit Bidirectional Universal Shift Registers

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Package / Case	Logic Type	Operating Temperature [Max]	Mounting Type	Supplier Device Package	Output Type	Number of Bits per Element	Function	Number of Elements	Package / Case [x]	Package / Case [y]
Texas Instruments SN74AS194N	4.5 V	5.5 V	0.3 in	16-DIP	7.62 mm	Register Bidirectional	70 °C	Through Hole	16-PDIP	Push-Pull	4	Universal	1
Texas Instruments SN74AS194D	4.5 V	5.5 V		16-SOIC		Register Bidirectional	70 °C	Surface Mount	16-SOIC	Push-Pull	4	Universal	1	0.154 in	3.9 mm
Texas Instruments SN74AS194DR	4.5 V	5.5 V		16-SOIC		Register Bidirectional	70 °C	Surface Mount	16-SOIC	Push-Pull	4	Universal	1	0.154 in	3.9 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 4.32
		100	$ 3.52
		250	$ 2.77
		1000	$ 2.35

Description

General part information

SN74AS194 Series

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

Documents

Technical documentation and resources

4-Bit Bidirectional Universal Shift Registers datasheet (Rev. A)

Data sheet