
ADS6444MRGCTEP
ActiveQUAD-CHANNEL, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) - ENHANCED-PRODUCT
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ADS6444MRGCTEP
ActiveQUAD-CHANNEL, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) - ENHANCED-PRODUCT
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Technical Specifications
Parameters and characteristics for this part
| Specification | ADS6444MRGCTEP |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Serial |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 4 |
| Number of Bits | 14 |
| Number of Inputs | 4 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 64-VFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 105 M |
| Supplier Device Package | 64-VQFN (9x9) |
| Voltage - Supply, Analog [Max] | 3.6 V |
| Voltage - Supply, Analog [Min] | 3 V |
| Voltage - Supply, Digital [Max] | 3.6 V |
| Voltage - Supply, Digital [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 250 | $ 194.30 | |
| Texas Instruments | SMALL T&R | 1 | $ 174.34 | |
| 100 | $ 157.81 | |||
| 250 | $ 153.30 | |||
| 1000 | $ 150.29 | |||
Description
General part information
ADS6444-EP Series
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.
Documents
Technical documentation and resources