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Texas Instruments-SN65DSI84ZXHR LVDS LVDS Receiver 1000Mbps 64-Pin NFBGA T/R
Integrated Circuits (ICs)

SN65DSI84ZXHR

Active
Texas Instruments

MIPI® DSI BRIDGE TO FLATLINK™ LVDS SINGLE-CHANNEL DSI TO DUAL-LINK LVDS BRIDGE

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Search across all available documentation for this part.

DocumentsDatasheetSN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide+3
Texas Instruments-SN65DSI84ZXHR LVDS LVDS Receiver 1000Mbps 64-Pin NFBGA T/R
Integrated Circuits (ICs)

SN65DSI84ZXHR

Active
Texas Instruments

MIPI® DSI BRIDGE TO FLATLINK™ LVDS SINGLE-CHANNEL DSI TO DUAL-LINK LVDS BRIDGE

Deep-Dive with AI

DocumentsDatasheetSN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide+3

Technical Specifications

Parameters and characteristics for this part

SpecificationSN65DSI84ZXHR
ApplicationsNotebook Computer
InterfaceLVDS, I2C, Serial
Mounting TypeSurface Mount
Package / Case64-VFBGA
Supplier Device Package64-NFBGA (5x5)
Voltage - Supply [Max]1.95 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 4.39
10$ 3.94
25$ 3.73
100$ 3.23
250$ 3.06
500$ 2.75
1000$ 2.32
Digi-Reel® 1$ 4.39
10$ 3.94
25$ 3.73
100$ 3.23
250$ 3.06
500$ 2.75
1000$ 2.32
Tape & Reel (TR) 2500$ 2.20
Texas InstrumentsLARGE T&R 1$ 3.31
100$ 2.90
250$ 2.04
1000$ 1.64

Description

General part information

SN65DSI84 Series

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.