Integrated Circuits (ICs)

8752CYLF

Obsolete

Renesas Electronics Corporation

LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

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Integrated Circuits (ICs)

8752CYLF

Obsolete

Renesas Electronics Corporation

LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	8752CYLF

Differential - Input:Output	False
Frequency - Max [Max]	240 MHz
Input	LVCMOS, LVTTL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output	LVCMOS, LVTTL
Package / Case	32-LQFP
PLL	Yes with Bypass
Ratio - Input:Output [custom]	8
Ratio - Input:Output [custom]	2
Supplier Device Package	32-TQFP (7x7)
Type	Zero Delay Buffer, Clock Multiplier
Voltage - Supply [Max]	3.465 V
Voltage - Supply [Min]	2.375 V

8752C Series

Low Skew, 1-to-8 LVCMOS Clock Multiplier/Zero Delay Buffer

Part	Mounting Type	Input	Output	Operating Temperature [Max]	Operating Temperature [Min]	Type	Package / Case	PLL	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Number of Circuits	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Differential - Input:Output	Frequency - Max [Max]
Renesas Electronics Corporation 8752CYLF	Surface Mount	LVCMOS LVTTL	LVCMOS LVTTL	70 °C	0 °C	Clock Multiplier Zero Delay Buffer	32-LQFP	Yes with Bypass	2.375 V	3.465 V	32-TQFP (7x7)	1	8	2		240 MHz

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

8752C Series

The 8752 is a low voltage, low skew LVCMOS clock generator. With output frequencies up to 240MHz, the 8752 is targeted for high performance clock applications. Along with a fully integrated PLL, the 8752 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".

Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.

For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state.

Documents

Technical documentation and resources