MC14044BDR2G
ActiveLATCH, MC14044, SR, TRI STATE, 120 NS, 8.8 MA, 16 PINS, SOIC
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MC14044BDR2G
ActiveLATCH, MC14044, SR, TRI STATE, 120 NS, 8.8 MA, 16 PINS, SOIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC14044BDR2G |
|---|---|
| Circuit | 1:1 |
| Current - Output High, Low [custom] | 8.8 mA |
| Current - Output High, Low [custom] | 8.8 mA |
| Delay Time - Propagation | 60 ns |
| Independent Circuits | 4 |
| Logic Type | S-R Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.13 | |
| 10 | $ 0.67 | |||
| 25 | $ 0.56 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.38 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Digi-Reel® | 1 | $ 1.13 | ||
| 10 | $ 0.67 | |||
| 25 | $ 0.56 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.38 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Tape & Reel (TR) | 2500 | $ 0.28 | ||
| 5000 | $ 0.26 | |||
| 7500 | $ 0.25 | |||
| 12500 | $ 0.24 | |||
| 17500 | $ 0.23 | |||
| 25000 | $ 0.23 | |||
| Newark | Each (Supplied on Cut Tape) | 1 | $ 0.87 | |
| 10 | $ 0.64 | |||
| 25 | $ 0.56 | |||
| 50 | $ 0.50 | |||
| 100 | $ 0.45 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.33 | |||
| ON Semiconductor | N/A | 1 | $ 0.24 | |
Description
General part information
MC14044B Series
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input; a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
Documents
Technical documentation and resources
