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Technical Specifications
Parameters and characteristics for this part
| Specification | ADS7866IDBVR |
|---|---|
| Architecture | SAR |
| Configuration | S/H-ADC |
| Data Interface | SPI |
| Input Type | Single Ended |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 12 bits |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | SOT-23-6 |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External |
| Sampling Rate (Per Second) | 200k |
| Supplier Device Package | SOT-23-6 |
| Voltage - Supply, Analog [Max] | 3.6 V |
| Voltage - Supply, Analog [Min] | 1.2 V |
| Voltage - Supply, Digital [Max] | 3.6 V |
| Voltage - Supply, Digital [Min] | 1.2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.68 | |
| 10 | $ 3.31 | |||
| 25 | $ 3.12 | |||
| 100 | $ 2.71 | |||
| 250 | $ 2.57 | |||
| 500 | $ 2.31 | |||
| 1000 | $ 1.94 | |||
| Digi-Reel® | 1 | $ 3.68 | ||
| 10 | $ 3.31 | |||
| 25 | $ 3.12 | |||
| 100 | $ 2.71 | |||
| 250 | $ 2.57 | |||
| 500 | $ 2.31 | |||
| 1000 | $ 1.94 | |||
| Tape & Reel (TR) | 3000 | $ 1.85 | ||
| Texas Instruments | LARGE T&R | 1 | $ 2.78 | |
| 100 | $ 2.43 | |||
| 250 | $ 1.71 | |||
| 1000 | $ 1.38 | |||
Description
General part information
ADS7866 Series
The ADS7866/67/68 are low power, miniature, 12/10/8-bit A/D converters each with a unipolar, single-ended input. These devices can operate from a single 1.6 V to 3.6 V supply with a 200-KSPS throughput for ADS7866. In addition, these devices can maintain at least a 100-KSPS throughput with a supply as low as 1.2 V.
The sampling, conversion, and activation of digital output SDO are initiated on the falling edge of CS\. The serial clock SCLK is used for controlling the conversion rate and shifting data out of the converter. Furthermore, SCLK provides a mechanism to allow digital host processors to synchronize with the con- verter. These converters interface with micro-processors or DSPs through a high-speed SPI compatible serial interface. There are no pipeline delays associated with the device.
The minimum conversion time is determined by the frequency of the serial clock input, SCLK, while the maximum frequency of SCLK is determined by the minimum sampling time required to charge the input capacitance to 12/10/8-bit accuracy for the ADS7866/67/68, respectively. The maximum throughput is determined by how often a conversion is initiated when the minimum sampling time is met and the maximum SCLK frequency is used. Each device automatically powers down after each conversion, which allows each device to save power when the throughput is reduced while using the maximum SCLK frequency.
Documents
Technical documentation and resources