Integrated Circuits (ICs)

CD74HC73M96

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HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET

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Search across all available documentation for this part.

DocumentsSignal Switch Data Book (Rev. A)CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)+13

Integrated Circuits (ICs)

CD74HC73M96

Active

Texas Instruments

HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET

Deep-Dive with AI

DocumentsSignal Switch Data Book (Rev. A)CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)+13

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CD74HC73M96

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	4 çA
Function	Reset
Input Capacitance	10 pF
Max Propagation Delay @ V, Max CL	28 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Trigger Type	Negative Edge
Type	JK Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

CD74HC73 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Part	Package / Case	Package / Case [y]	Package / Case [x]	Function	Current - Quiescent (Iq)	Type	Input Capacitance	Max Propagation Delay @ V, Max CL	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Number of Bits per Element	Clock Frequency	Output Type	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments CD74HC73EG4	14-DIP	7.62 mm	0.3 "	Reset	4 çA	JK Type	10 pF	28 ns	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	Through Hole	1	60 MHz	Complementary	2	125 °C	-55 °C
Texas Instruments CD74HC73M	14-SOIC	3.9 mm	0.154 in	Reset	4 çA	JK Type	10 pF	28 ns	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	Surface Mount	1	60 MHz	Complementary	2	125 °C	-55 °C
Texas Instruments CD74HC73MT	14-SOIC	3.9 mm	0.154 in	Reset	4 çA	JK Type	10 pF	28 ns	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	Surface Mount	1	60 MHz	Complementary	2	125 °C	-55 °C
Texas Instruments CD74HC73M96	14-SOIC	3.9 mm	0.154 in	Reset	4 çA	JK Type	10 pF	28 ns	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	Surface Mount	1	60 MHz	Complementary	2	125 °C	-55 °C
Texas Instruments CD74HC73E	14-DIP	7.62 mm	0.3 "	Reset	4 çA	JK Type	10 pF	28 ns	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	Through Hole	1	60 MHz	Complementary	2	125 °C	-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.51
		10	$ 0.41
		25	$ 0.38
		100	$ 0.28
		250	$ 0.25
		500	$ 0.21
		1000	$ 0.16
	Digi-Reel®	1	$ 0.51
		10	$ 0.41
		25	$ 0.38
		100	$ 0.28
		250	$ 0.25
		500	$ 0.21
		1000	$ 0.16
	Tape & Reel (TR)	2500	$ 0.14
		5000	$ 0.14
		12500	$ 0.13
		25000	$ 0.12
		62500	$ 0.11
Texas Instruments	LARGE T&R	1	$ 0.25
		100	$ 0.17
		250	$ 0.13
		1000	$ 0.09

Description

General part information

CD74HC73 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Documents

Technical documentation and resources

Signal Switch Data Book (Rev. A)

User guide

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)

Data sheet

CD74HC73M96

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CD74HC73M96

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Technical Specifications

CD74HC73 Series

Pricing

Description

CD74HC73 Series

Documents

Signal Switch Data Book (Rev. A)

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

SN54/74HCT CMOS Logic Family Applications and Restrictions

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Input and Output Characteristics of Digital Integrated Circuits

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Logic Guide (Rev. AB)

TI IBIS File Creation, Validation, and Distribution Processes

Designing With Logic (Rev. C)

LOGIC Pocket Data Book (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Live Insertion

CD74HC73 Series