LMH0051SQE/NOPB
ActiveHD/ SD/ DVB-ASI SDI DESERIALZIER WITH LVDS INTERFACE
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LMH0051SQE/NOPB
ActiveHD/ SD/ DVB-ASI SDI DESERIALZIER WITH LVDS INTERFACE
Technical Specifications
Parameters and characteristics for this part
| Specification | LMH0051SQE/NOPB |
|---|---|
| Data Rate | 2.97 Gbps |
| Function | Deserializer |
| Input Type | LVCMOS |
| Mounting Type | Surface Mount |
| Number of Inputs | 2 |
| Number of Outputs | 5 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | LVDS |
| Package / Case | 48-WFQFN Exposed Pad |
| Supplier Device Package | 48-WQFN (7x7) |
| Voltage - Supply | 2.5 V, 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 28.69 | |
| Digi-Reel® | 1 | $ 28.69 | ||
| Tape & Reel (TR) | 250 | $ 21.55 | ||
| Texas Instruments | SMALL T&R | 1 | $ 22.52 | |
| 100 | $ 20.02 | |||
| 250 | $ 16.45 | |||
| 1000 | $ 14.72 | |||
Description
General part information
LMH0051 Series
The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
Documents
Technical documentation and resources