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Technical Specifications
Parameters and characteristics for this part
| Specification | TSB82AA2BPGE |
|---|---|
| Function | Link Layer Controller |
| Interface | PCI |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 144-LQFP |
| Protocol | IEEE 1394 |
| Standards | OHCI-Lynx™, IEEE 1394a-2000 |
| Supplier Device Package | 144-LQFP (20x20) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 120 | $ 12.83 | |
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 12.94 | |
| 100 | $ 11.30 | |||
| 250 | $ 8.72 | |||
| 1000 | $ 7.80 | |||
Description
General part information
TSB82AA2-EP Series
The TSB82AA2B OHCI-Lynx. controller is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today's 1394 bus designs. The TSB82AA2B device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2B device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.
The TSB82AA2B improved throughput and increased bandwidth make it ideal for today's high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.
The TSB82AA2B OHCI-Lynx controller operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2B device is capable of multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.
Documents
Technical documentation and resources