Specification	TSB43AB23PGE

Function	Physical Layer Controller
Interface	PCI
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Package / Case	144-LQFP
Protocol	IEEE 1394
Standards	i.Link™, IEEE 1394-1995, Firewire™, 1394a-2000, OHCI
Supplier Device Package	144-LQFP (20x20)
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

TSB43AB23-EP Series

Enhanced product IEEE 1394a-2000 OHCI PHY/link layer controller

Part	Protocol	Package / Case	Supplier Device Package	Function	Standards	Interface	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments TSB43AB23PGE	IEEE 1394	144-LQFP	144-LQFP (20x20)	Physical Layer Controller	1394a-2000 Firewire™ i.Link™ IEEE 1394-1995 OHCI	PCI	70 °C	0 °C	3.6 V	3 V
Texas Instruments TSB43AB23IPDTEP	IEEE 1394	128-TQFP		Physical Layer Controller	1394a-2000 Firewire™ i.Link™ IEEE 1394-1995 OHCI	PCI	85 °C	-40 °C	3.6 V	3 V
Texas Instruments TSB43AB23PDTG4	IEEE 1394	128-TQFP		Physical Layer Controller	1394a-2000 Firewire™ i.Link™ IEEE 1394-1995 OHCI	PCI	70 °C	0 °C	3.6 V	3 V
Texas Instruments TSB43AB23PDT	IEEE 1394	128-TQFP		Physical Layer Controller	1394a-2000 Firewire™ i.Link™ IEEE 1394-1995 OHCI	PCI	70 °C	0 °C	3.6 V	3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	JEDEC TRAY (10+1)	1	$ 7.84
		100	$ 6.39
		250	$ 5.02
		1000	$ 4.26

Description

General part information

TSB43AB23-EP Series

The Texas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with thePCI Local Bus Specification, thePCI Bus Power Management Interface Specification(Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the1394 Open Host Controller Interface Specification(Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 device provides three 1394 ports that have separate cable bias (TPBIAS). The TSB43AB23 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB23 device is compliant with thePCI Bus Power Management Interface Specificationas specified by thePC 2001 Design Guiderequirements. The TSB43AB23 device supports the D0, D1, D2, and D3 power states.

The TSB43AB23 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data.

Documents

Technical documentation and resources

IEEE 1394a-2000 OHCI PHY/Link Layer Controller datasheet (Rev. A)

Data sheet