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CD74FCT623M

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Texas Instruments

BICMOS FCT INTERFACE LOGIC OCTAL NON-INVERTING BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SOIC (DW)
Integrated Circuits (ICs)

CD74FCT623M

Active
Texas Instruments

BICMOS FCT INTERFACE LOGIC OCTAL NON-INVERTING BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74FCT623M
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]15 mA
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output Type3-State
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 6.66
10$ 6.02
25$ 5.74
75$ 4.00
100$ 4.98
250$ 4.76
500$ 4.34
1000$ 3.78
2500$ 3.64
Texas InstrumentsTUBE 1$ 5.87
100$ 4.78
250$ 3.76
1000$ 3.19

Description

General part information

CD74FCT623 Series

The CD74FCT623 is an octal bus transceiver that uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCCbounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA.

This device is a noninverting, 3-state, bidirectional transceiver-buffer intended for two-way transmission from A bus to B bus or B bus to A bus, depending on the logic levels of the output-enable (OEAB, OEBA\) inputs.

The dual output-enable provision gives these devices the capability to store data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input under these conditions, and when all other data sources to the bus lines are at high impedance, both sets of bus lines remain in their last states.

Documents

Technical documentation and resources