
NC7SV57FHX
ActiveTINYLOGIC ULP-A UNIVERSAL CONFIGURABLE 2-INPUT LOGIC GATES
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NC7SV57FHX
ActiveTINYLOGIC ULP-A UNIVERSAL CONFIGURABLE 2-INPUT LOGIC GATES
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Technical Specifications
Parameters and characteristics for this part
| Specification | NC7SV57FHX |
|---|---|
| Current - Output High, Low | 24 mA |
| Logic Type | Configurable Multiple Function |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Number of Inputs | 3 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Single-Ended |
| Package / Case | 6-UFDFN |
| Schmitt Trigger Input | False |
| Supplier Device Package | 6-MicroPak2™ |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 0.9 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 1578 | $ 0.19 | |
Description
General part information
NC7SV57 Series
The NC7SV57 and NC7SV58 are universal configurable two-input logic gates from ON Semiconductor’s Ultra-Low Power (ULP-A) series of TinyLogic® . ULP-A is ideal for applications that require extreme high-speed, high drive, and low power. This product is designed for a wide low-voltage operating range (0.9V to 3.6V VCC) and applications that require more drive and speed than the TinyLogic ULP series, but still offer best-in-class, low-power operation.Each device is capable of being configured for 1 of 5 unique two-input logic functions. Any possible two-input combinatorial logic function can be implemented, as shown in the Function Selection Table. Device functionality is selected by how the device is wired at the board level. Figures 1 through 10 illustrate how to connect the NC7SV57 and NC7SV58, respectively, for the desired logic function. All inputs have been implemented with hysteresis.The NC7SV57 and NC7SV58 are uniquely designed for optimized power and speed and are fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation.
Documents
Technical documentation and resources