Specification	SNJ54ABT823FK

Clock Frequency	200 MHz
Current - Output High, Low [custom]	24 mA
Current - Output High, Low [custom]	48 mA
Current - Quiescent (Iq)	38 mA
Input Capacitance	4 pF
Max Propagation Delay @ V, Max CL	6.1 ns
Mounting Type	Surface Mount
Number of Bits per Element	9
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Tri-State, Non-Inverted
Package / Case	28-CLCC
Supplier Device Package	28-LCCC
Supplier Device Package [x]	11.43
Supplier Device Package [y]	11.43
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN54ABT823 Series

9-Bit Bus-Interface Flip-Flops With 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Number of Elements	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]	Current - Quiescent (Iq)	Package / Case	Clock Frequency	Voltage - Supply [Min]	Voltage - Supply [Max]	Max Propagation Delay @ V, Max CL	Output Type	Mounting Type	Trigger Type	Type	Input Capacitance	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SNJ54ABT823FK	24 mA	48 mA	9	1	11.43	28-LCCC	11.43	38 mA	28-CLCC	200 MHz	4.5 V	5.5 V	6.1 ns	Non-Inverted Tri-State	Surface Mount	Positive Edge	D-Type	4 pF	125 °C	-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 58.62
		100	$ 52.10
		250	$ 42.83
		1000	$ 38.31

Description

General part information

SN54ABT823 Series

These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN\) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the nine Q outputs to go low, independently of the clock.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

SNJ54ABT823FK

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SNJ54ABT823FK

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Technical Specifications

SN54ABT823 Series

Pricing

Description

SN54ABT823 Series

Documents

Datasheet

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Input and Output Characteristics of Digital Integrated Circuits

TI IBIS File Creation, Validation, and Distribution Processes

Advanced Bus Interface Logic Selection Guide

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Live Insertion

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Selecting the Right Level Translation Solution (Rev. A)

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Logic Guide (Rev. AB)

Designing With Logic (Rev. C)

Quad Flatpack No-Lead Logic Packages (Rev. D)

LOGIC Pocket Data Book (Rev. B)

SN54ABT823 Series