CY54FCT373ATDMB
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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CY54FCT373ATDMB
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CY54FCT373ATDMB |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 32 mA |
| Delay Time - Propagation | 9.8 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-CDIP |
| Supplier Device Package | 20-CDIP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 23.11 | |
| 100 | $ 20.18 | |||
| 250 | $ 15.56 | |||
| 1000 | $ 13.92 | |||
Description
General part information
CY54FCT373T Series
The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
Documents
Technical documentation and resources