SN74ALVC162835DL
UnknownBUS XCVR SINGLE 18-CH 3-ST 56-PIN SSOP TUBE
Deep-Dive with AI
Search across all available documentation for this part.
SN74ALVC162835DL
UnknownBUS XCVR SINGLE 18-CH 3-ST 56-PIN SSOP TUBE
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVC162835DL |
|---|---|
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Logic Type | Universal Bus Driver |
| Mounting Type | Surface Mount |
| Number of Circuits | 18 Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 0.295 in |
| Package / Case | 56-BSSOP |
| Package / Case | 7.5 mm |
| Supplier Device Package | 56-SSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 460 | $ 0.97 | |
Description
General part information
SN74ALVC162835 Series
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Documents
Technical documentation and resources
No documents available
