ADC09DJ800AAVTQ1
ActiveAUTOMOTIVE DUAL-CHANNEL, 9-BIT, 800-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE
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ADC09DJ800AAVTQ1
ActiveAUTOMOTIVE DUAL-CHANNEL, 9-BIT, 800-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE
Technical Specifications
Parameters and characteristics for this part
| Specification | ADC09DJ800AAVTQ1 |
|---|---|
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Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 250 | $ 36.75 | |
| Texas Instruments | SMALL T&R | 1 | $ 39.77 | |
| 100 | $ 35.35 | |||
| 250 | $ 29.06 | |||
| 1000 | $ 25.99 | |||
Description
General part information
ADC09DJ800-Q1 Series
ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
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