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10-VSSOP
Integrated Circuits (ICs)

LMP91050MMX/NOPB

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Texas Instruments

CONFIGURABLE AFE FOR NONDISPERSIVE INFRARED (NDIR) SENSING APPLICATIONS

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10-VSSOP
Integrated Circuits (ICs)

LMP91050MMX/NOPB

Active
Texas Instruments

CONFIGURABLE AFE FOR NONDISPERSIVE INFRARED (NDIR) SENSING APPLICATIONS

Technical Specifications

Parameters and characteristics for this part

SpecificationLMP91050MMX/NOPB
Mounting TypeSurface Mount
Number of Channels1
Package / Case10-MSOP, 10-TFSOP
Package / Case [x]3 mm
Package / Case [x]0.118 in
Supplier Device Package10-VSSOP
Voltage - Supply, Analog [Max]5.5 V
Voltage - Supply, Analog [Min]2.7 V
Voltage - Supply, Digital [Max]5.5 V
Voltage - Supply, Digital [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.35
10$ 3.00
25$ 2.84
100$ 2.46
250$ 2.34
500$ 2.10
1000$ 1.77
Digi-Reel® 1$ 3.35
10$ 3.00
25$ 2.84
100$ 2.46
250$ 2.34
500$ 2.10
1000$ 1.77
Tape & Reel (TR) 3500$ 1.60
Texas InstrumentsLARGE T&R 1$ 2.52
100$ 2.21
250$ 1.55
1000$ 1.25

Description

General part information

LMP91050 Series

The LMP91050 device is a programmable integrated Sensor Analog Front End (AFE) optimized for thermopile sensors, as typically used in NDIR applications. It provides a complete signal path solution between a sensor and microcontroller that generates an output voltage proportional to the thermopile voltage. The programmability of the LMP91050 enables it to support multiple thermopile sensors with a single design as opposed to the multiple discrete solutions.

The LMP91050 features a programmable gain amplifier (PGA),dark phaseoffset cancellation, and an adjustable common-mode generator (1.15 V or 2.59 V) which increases output dynamic range. The PGA offers a low-gain range of 167 V/V to 1335 V/V plus a high-gain range of 1002 V/V to 7986 V/V which enables the user to use thermopiles with different sensitivities. The PGA is highlighted by low-gain drift (100 ppm/°C), output offset drift (1.2 mV/°C at G = 1002 V/V), phase delay drift (500 ns) and noise specifications (0.1 µVRMS0.1 to 10Hz).

The offset cancellation circuitry compensates for the by adding an equal and opposite offset to the input of the second stage, thus removing the original offset from the output signal. This offset cancellation circuitry allows optimized usage of the ADC full scale and relaxes ADC resolution requirements.