The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls, software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, selectable hardware or software autoflow control features can significantly reduce program overload and increase system efficiency by automatically controlling serial data flow.Read more