
ADC12QJ800AAVT
ActiveQUAD-CHANNEL, 12-BIT, 800-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE
Deep-Dive with AI
Search across all available documentation for this part.

ADC12QJ800AAVT
ActiveQUAD-CHANNEL, 12-BIT, 800-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC) WITH JESD204C INTERFACE
Technical Specifications
Parameters and characteristics for this part
| Specification | ADC12QJ800AAVT |
|---|---|
| Architecture | Pipelined, SAR |
| Configuration | ADC |
| Data Interface | JESD204B/C |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 4 |
| Number of Bits | 12 bits |
| Number of Inputs | 4 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | FCBGA, 144-FBGA |
| Ratio - S/H:ADC | 0:4 |
| Sampling Rate (Per Second) | 800 M |
| Supplier Device Package | 144-FCBGA (10x10) |
| Voltage - Supply, Analog [Max] | 2 V, 1.15 V |
| Voltage - Supply, Analog [Min] | 1.8 V, 1.05 V |
| Voltage - Supply, Digital [Max] | 1.15 V |
| Voltage - Supply, Digital [Min] | 1.05 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 250 | $ 177.11 | |
| Texas Instruments | SMALL T&R | 1 | $ 158.92 | |
| 100 | $ 143.85 | |||
| 250 | $ 139.74 | |||
| 1000 | $ 137.00 | |||
Description
General part information
ADC12QJ800 Series
ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
Documents
Technical documentation and resources