Specification	CD54HCT4046AF3A

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	38 MHz
Input	CMOS
Mounting Type	Through Hole
Number of Circuits	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output	CMOS
Package / Case	7.62 mm, 0.3 in
Package / Case	16-CDIP
PLL	True
Ratio - Input:Output	1:4
Supplier Device Package	16-CDIP
Type	Phase Lock Loop (PLL)
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

CD54HCT4046A Series

High Speed CMOS Logic Phase-Locked-Loop with VCO

Part	Input	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Output	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Ratio - Input:Output	Type	PLL	Number of Circuits	Differential - Input:Output	Frequency - Max [Max]	Supplier Device Package	Divider/Multiplier
Texas Instruments CD54HCT4046AF3A	CMOS	Through Hole	4.5 V	5.5 V	CMOS	125 °C	-55 °C	0.3 in 7.62 mm	16-CDIP	1:4	Phase Lock Loop (PLL)		1		38 MHz	16-CDIP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 46.53
		100	$ 41.36
		250	$ 34.00
		1000	$ 30.41

Description

General part information

CD54HCT4046A Series

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

Documents

Technical documentation and resources

Datasheet

CD54HCT4046AF3A

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CD54HCT4046AF3A

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Technical Specifications

CD54HCT4046A Series

Pricing

Description

CD54HCT4046A Series

Documents

Datasheet

TI IBIS File Creation, Validation, and Distribution Processes

Designing With Logic (Rev. C)

LOGIC Pocket Data Book (Rev. B)

Signal Switch Data Book (Rev. A)

Implementation of FSK Modulation and Demodulation using CD74HC4046A

Logic Guide (Rev. AB)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

SN54/74HCT CMOS Logic Family Applications and Restrictions

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

CMOS Phase-Locked-Loop Applications (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

CMOS Power Consumption and CPD Calculation (Rev. B)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

CD54HCT4046A Series