SN74ABT16374ADL
Active16-BIT EDGE-TRIGGERED D-TYPE FFLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74ABT16374ADL
Active16-BIT EDGE-TRIGGERED D-TYPE FFLIP-FLOPS WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ABT16374ADL |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Current - Quiescent (Iq) | 2 mA |
| Function | Standard |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 4.7 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 48-BSSOP |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 48-SSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 2.04 | |
| 10 | $ 1.83 | |||
| 25 | $ 1.73 | |||
| 100 | $ 1.47 | |||
| 250 | $ 1.38 | |||
| 500 | $ 1.21 | |||
| 1000 | $ 1.00 | |||
| 2500 | $ 0.93 | |||
| 5000 | $ 0.90 | |||
| Texas Instruments | TUBE | 1 | $ 1.53 | |
| 100 | $ 1.27 | |||
| 250 | $ 0.91 | |||
| 1000 | $ 0.69 | |||
Description
General part information
SN74ABT16374A Series
The 'ABT16374A are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components
Documents
Technical documentation and resources