8543BGILF
ObsoleteLOW SKEW,1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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8543BGILF
ObsoleteLOW SKEW,1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 8543BGILF |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 650 MHz |
| Input | SSTL, CML, LVDS, HCSL, LVHSTL, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVDS |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Ratio - Input:Output [custom] | 2:4 |
| Supplier Device Package | 20-TSSOP |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
8543B Series
The 8543I is a low-skew, high-performance 1-to-4 differential-to-LVDS clock fanout buffer. Utilizing low voltage differential signaling (LVDS) the 8543I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The 8543I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the 8543I ideal for those applications demanding well-defined performance and repeatability.
Documents
Technical documentation and resources