Integrated Circuits (ICs)

SN74ACT00NSR

Active

4-CH, 2-INPUT, 4.5-V TO 5.5-V NAND GATES WITH TTL-COMPATIBLE CMOS INPUTS

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Search across all available documentation for this part.

DocumentsImplications of Slow or Floating CMOS Inputs (Rev. E)SNx4ACT00 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. F)+9

Integrated Circuits (ICs)

SN74ACT00NSR

Active

Texas Instruments

4-CH, 2-INPUT, 4.5-V TO 5.5-V NAND GATES WITH TTL-COMPATIBLE CMOS INPUTS

Deep-Dive with AI

DocumentsImplications of Slow or Floating CMOS Inputs (Rev. E)SNx4ACT00 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. F)+9

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74ACT00NSR

Current - Output High, Low	24 mA
Input Logic Level - Low	0.8 V
Logic Type	NAND Gate
Max Propagation Delay @ V, Max CL	9 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	14-SOIC
Package / Case [x]	0.209 "
Package / Case [y]	5.3 mm
Supplier Device Package	14-SO
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ACT00-Q1 Series

Automotive, 4-ch, 2-input, 4.5V to 5.5V NAND gates with TTL-compatible CMOS inputs

Part	Max Propagation Delay @ V, Max CL	Logic Type	Current - Output High, Low	Input Logic Level - Low	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case [x]	Package / Case [y]	Package / Case	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Current - Quiescent (Max) [Max]	Number of Inputs	Number of Circuits	Qualification	Grade	Package / Case [custom]	Package / Case [custom]	Supplier Device Package	Package / Case	Package / Case
Texas Instruments CD74ACT00M	13.2 ns	NAND Gate	24 mA	0.8 V	-55 °C	125 °C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount	4 µA	2	4
Texas Instruments SN74ACT00TDRQ1	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	105 ░C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4	AEC-Q100	Automotive
Texas Instruments SN74ACT00PW	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C			14-TSSOP	4.5 V	5.5 V	Surface Mount		2	4			0.173 "	4.4 mm	14-TSSOP
Texas Instruments SN74ACT00DG4	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4
Texas Instruments SN74ACT00DRG4	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4
Texas Instruments SN74ACT00D	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4
Texas Instruments SN74ACT00NSR	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C	0.209 "	5.3 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4					14-SO
Texas Instruments CD74ACT00E	13.2 ns	NAND Gate	24 mA	0.8 V	-55 °C	125 °C	0.3 "	7.62 mm	14-DIP	4.5 V	5.5 V	Through Hole	4 µA	2	4
Texas Instruments SN74ACT00DR	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C	0.154 in	3.9 mm	14-SOIC	4.5 V	5.5 V	Surface Mount		2	4
Texas Instruments SN74ACT00DBR	9 ns	NAND Gate	24 mA	0.8 V	-40 °C	85 °C			14-SSOP	4.5 V	5.5 V	Surface Mount		2	4					14-SSOP	5.3 mm	0.209 "

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.81
		10	$ 0.71
		25	$ 0.67
		100	$ 0.54
		250	$ 0.51
		500	$ 0.43
		1000	$ 0.34
	Digi-Reel®	1	$ 0.81
		10	$ 0.71
		25	$ 0.67
		100	$ 0.54
		250	$ 0.51
		500	$ 0.43
		1000	$ 0.34
	Tape & Reel (TR)	2000	$ 0.27
Texas Instruments	LARGE T&R	1	$ 0.67
		100	$ 0.46
		250	$ 0.35
		1000	$ 0.23

Description

General part information

SN74ACT00-Q1 Series

The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A•B or Y = A+B in positive logic.

Documents

Technical documentation and resources

SN74ACT00NSR

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SN74ACT00NSR

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Technical Specifications

SN74ACT00-Q1 Series

Pricing

Description

SN74ACT00-Q1 Series

Documents

Implications of Slow or Floating CMOS Inputs (Rev. E)

SNx4ACT00 Quadruple 2-Input Positive-NAND Gates datasheet (Rev. F)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Logic Guide (Rev. AB)

Selecting the Right Level Translation Solution (Rev. A)

CMOS Power Consumption and CPD Calculation (Rev. B)

Designing With Logic (Rev. C)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

TI IBIS File Creation, Validation, and Distribution Processes

LOGIC Pocket Data Book (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

SN74ACT00-Q1 Series