FPC401RHUR
ActiveQUAD PORT CONTROLLER I2C/SPI INTERFACE 2.5V 56-PIN WQFN EP T/R
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FPC401RHUR
ActiveQUAD PORT CONTROLLER I2C/SPI INTERFACE 2.5V 56-PIN WQFN EP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | FPC401RHUR |
|---|---|
| Applications | Controller |
| Interface | I2C |
| Mounting Type | Surface Mount |
| Package / Case | 56-WFQFN Exposed Pad |
| Supplier Device Package | 56-WQFN (5x11) |
| Voltage - Supply [Max] | 3.3 V |
| Voltage - Supply [Min] | 1.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 3.81 | |
| Texas Instruments | LARGE T&R | 1 | $ 5.34 | |
| 100 | $ 4.36 | |||
| 250 | $ 3.42 | |||
| 1000 | $ 2.90 | |||
Description
General part information
FPC401 Series
The FPC401 quad port controller serves as a low-speed signal aggregator for common port types such as SFP+, QSFP+, and SAS. The FPC401 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC401s can be used in high-port-count applications with one common control interface to the host. The FPC401 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the ports’ low-speed signals cuts system BOM cost by enabling the use of smaller IO count control devices (FPGAs, CPLDs, MCUs) and by reducing routing layer congestion.
The FPC401 quad port controller serves as a low-speed signal aggregator for common port types such as SFP+, QSFP+, and SAS. The FPC401 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC401s can be used in high-port-count applications with one common control interface to the host. The FPC401 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the ports’ low-speed signals cuts system BOM cost by enabling the use of smaller IO count control devices (FPGAs, CPLDs, MCUs) and by reducing routing layer congestion.
Documents
Technical documentation and resources
