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74ACT11074N

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Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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PDIP (N)
Integrated Circuits (ICs)

74ACT11074N

Active
Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics for this part

Specification74ACT11074N
Clock Frequency125 MHz
Current - Output High, Low [custom]24 mA
Current - Output High, Low [custom]24 mA
Current - Quiescent (Iq)4 çA
FunctionSet(Preset) and Reset
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL8.5 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]85 C
Operating Temperature [Min]-40 ¯C
Output TypeComplementary
Package / Case14-DIP
Package / Case0.3 in
Package / Case7.62 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V
PartPackage / Case [x]Package / Case [y]Package / CaseOperating Temperature [Max]Operating Temperature [Min]Mounting TypeSupplier Device PackageCurrent - Quiescent (Iq)TypeFunctionNumber of ElementsVoltage - Supply [Max]Voltage - Supply [Min]Current - Output High, Low [custom]Current - Output High, Low [custom]Trigger TypeOutput TypeClock FrequencyNumber of Bits per ElementInput CapacitanceMax Propagation Delay @ V, Max CLPackage / CasePackage / CasePackage / CasePackage / Case [custom]Package / Case [custom]
Texas Instruments-SN74HC32NSRG4 Logic Gates OR Gate 4-Element 2-IN CMOS 14-Pin SOP T/R
Texas Instruments
0.209 in
5.3 mm
14-SOIC
85 C
-40 ¯C
Surface Mount
14-SO
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
PDIP (N)
Texas Instruments
14-DIP
85 C
-40 ¯C
Through Hole
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.3 in
7.62 mm
14-SOIC
Texas Instruments
14-SOIC
85 C
-40 ¯C
Surface Mount
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.154 in
3.9 mm
14-SOIC
Texas Instruments
14-SOIC
85 C
-40 ¯C
Surface Mount
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.154 in
3.9 mm
SSOP (DB)
Texas Instruments
14-SSOP
85 C
-40 ¯C
Surface Mount
14-SSOP
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.209 in
5.3 mm
14-Dip
Texas Instruments
14-DIP
85 C
-40 ¯C
Through Hole
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.3 in
7.62 mm
14-SOIC
Texas Instruments
14-SOIC
85 C
-40 ¯C
Surface Mount
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.154 in
3.9 mm
14-SOIC
Texas Instruments
14-SOIC
85 C
-40 ¯C
Surface Mount
4 çA
D-Type
Set(Preset) and Reset
2
5.5 V
4.5 V
24 mA
24 mA
Positive Edge
Complementary
125 MHz
1
3.5 pF
8.5 ns
0.154 in
3.9 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 25$ 1.44
DigikeyN/A 0$ 3.61
41409$ 3.61
Tube 1$ 1.99
10$ 1.79
25$ 1.69
100$ 1.44
250$ 1.35
500$ 1.19
Texas InstrumentsTUBE 1$ 2.77
100$ 2.29
250$ 1.65
1000$ 1.24

Description

General part information

74ACT11074 Series

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from -40°C to 85°C.

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.