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SOIC (D)
Integrated Circuits (ICs)

CD74HCT4520M96

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Texas Instruments

HIGH SPEED CMOS LOGIC DUAL BINARY UP-COUNTERS

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SOIC (D)
Integrated Circuits (ICs)

CD74HCT4520M96

Active
Texas Instruments

HIGH SPEED CMOS LOGIC DUAL BINARY UP-COUNTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HCT4520M96
Count Rate25 MHz
DirectionUp
Logic TypeBinary Counter
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
TimingSynchronous
Trigger TypeNegative, Positive
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 1283$ 0.23
Cut Tape (CT) 1$ 0.73
10$ 0.65
25$ 0.61
100$ 0.50
250$ 0.46
500$ 0.39
1000$ 0.31
Digi-Reel® 1$ 0.73
10$ 0.65
25$ 0.61
100$ 0.50
250$ 0.46
500$ 0.39
1000$ 0.31
Tape & Reel (TR) 2500$ 0.20
Texas InstrumentsLARGE T&R 1$ 0.51
100$ 0.35
250$ 0.27
1000$ 0.18

Description

General part information

CD74HCT4520 Series

The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.

The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.