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Texas Instruments-ADC34J44IRGZT Analog to Digital Converters - ADCs 4-Channel Quad ADC Pipelined 125Msps 14-bit JESD204B 48-Pin VQFN EP T/R
Integrated Circuits (ICs)

ADS61B49IRGZT

Active
Texas Instruments

1-CHANNEL SINGLE ADC PIPELINED 250MSPS 14-BIT PARALLEL/LVDS 48-PIN VQFN EP T/R

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Texas Instruments-ADC34J44IRGZT Analog to Digital Converters - ADCs 4-Channel Quad ADC Pipelined 125Msps 14-bit JESD204B 48-Pin VQFN EP T/R
Integrated Circuits (ICs)

ADS61B49IRGZT

Active
Texas Instruments

1-CHANNEL SINGLE ADC PIPELINED 250MSPS 14-BIT PARALLEL/LVDS 48-PIN VQFN EP T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationADS61B49IRGZT
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Parallel, Parallel
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits14
Number of Inputs1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case48-VFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)250 M
Supplier Device Package48-VQFN (7x7)
Voltage - Supply, Analog [Max]3.6 V
Voltage - Supply, Analog [Min]3 V
Voltage - Supply, Digital [Max]1.9 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 189.79
Digi-Reel® 1$ 189.79
Tape & Reel (TR) 250$ 171.08
Texas InstrumentsSMALL T&R 1$ 176.19
100$ 159.48
250$ 154.92
1000$ 151.88

Description

General part information

ADS61B49 Series

The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).