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Integrated Circuits (ICs)

SN75ALS164DWR

Obsolete
Texas Instruments

OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

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SOIC (DW)
Integrated Circuits (ICs)

SN75ALS164DWR

Obsolete
Texas Instruments

OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

Technical Specifications

Parameters and characteristics for this part

SpecificationSN75ALS164DWR
DuplexHalf
Mounting TypeSurface Mount
Number of Drivers/Receivers [custom]8
Number of Drivers/Receivers [custom]8
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
ProtocolIEEE 488
Receiver Hysteresis650 mV
Supplier Device Package24-SOIC
TypeTransceiver
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsLARGE T&R 1$ 7.32
100$ 5.96
250$ 4.69
1000$ 3.98

Description

General part information

SN75ALS164 Series

The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus.

The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during VCCpower-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output.

The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCCis 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the terminal when disabled.