Integrated Circuits (ICs)

74LVT573D,112

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NXP USA Inc.

IC D-TYPE TRANSP SGL 8:8 20SO

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Integrated Circuits (ICs)

74LVT573D,112

Active

NXP USA Inc.

IC D-TYPE TRANSP SGL 8:8 20SO

Deep-Dive with AI

Specifications Series Pricing CAD Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	74LVT573D,112

Circuit	8:8
Current - Output High	32 mA
Current - Output Low	64 mA
Delay Time - Propagation	2.7 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature (Max)	85 °C
Operating Temperature (Min)	-40 °C
Output Type	Tri-State
Package Length	0.295 in
Package Name	20-SO, 20-SOIC
Package Width	7.5 mm
Voltage - Supply (Maximum)	3.6 V
Voltage - Supply (Minimum)	2.7 V

74LVT573 Series

Low Voltage Octal Transparent Latch with 3-STATE Outputs

Part	Package / Case	Independent Circuits	Mounting Type	Current - Output High	Current - Output Low	Package Length	Package Name	Package Width	Delay Time - Propagation	Output Type	Circuit	Operating Temperature (Min)	Operating Temperature (Max)	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Logic Type
NXP USA Inc. 74LVT573BQ,115	20-VFQFN Exposed Pad	1	Surface Mount	32 mA	64 mA	4.5 mm	20-DHVQFN	2.5 mm	2.7 ns	Tri-State	8:8	-40 °C	85 °C	3.6 V	2.7 V	D-Type Transparent Latch
NXP USA Inc. 74LVT573D,112		1	Surface Mount	32 mA	64 mA	0.295 in	20-SO 20-SOIC	7.5 mm	2.7 ns	Tri-State	8:8	-40 °C	85 °C	3.6 V	2.7 V	D-Type Transparent Latch
NXP USA Inc. 74LVT573PW/AUJ		1	Surface Mount	32 mA	64 mA	0.173 in	20-TSSOP	4.4 mm	2.7 ns	Tri-State	8:8	-40 °C	85 °C	3.6 V	2.7 V	D-Type Transparent Latch

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$	Updated

CAD

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Description

General part information

74LVT573 Series

The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state. The LVTH573 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal latches are designed for low-voltage (3.3V) VCCapplications, but with the capability to provide a TTL interface to a 5V environment. The LVT573 and LVTH573 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.

Documents

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