CS48L10-CNZR
NRNDDSP FIXED-POINT 32-BIT 120MHZ 24-PIN QFN T/R
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CS48L10-CNZR
NRNDDSP FIXED-POINT 32-BIT 120MHZ 24-PIN QFN T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | CS48L10-CNZR |
|---|---|
| Clock Rate | 80 MHz |
| Interface | I2C, SPI |
| Mounting Type | Surface Mount |
| Non-Volatile Memory | 160 kB |
| On-Chip RAM | 2 Mbit |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 24-VFQFN Exposed Pad |
| Supplier Device Package | 24-QFN |
| Type | Fixed Point |
| Voltage - Core [custom] | 1 V |
| Voltage - I/O | 3.3 V, 1.8 V |
CS48L10 Series
| Part | Interface | Clock Rate | Voltage - I/O | Package / Case | Voltage - Core [custom] | On-Chip RAM | Supplier Device Package | Operating Temperature [Max] | Operating Temperature [Min] | Non-Volatile Memory | Mounting Type | Type | Voltage - Core |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Cirrus Logic Inc. | I2C SPI | 80 MHz | 1.8 V 3.3 V | 24-VFQFN Exposed Pad | 1 V | 2 Mbit | 24-QFN | 70 °C | 0 °C | 160 kB | Surface Mount | Fixed Point | |
Cirrus Logic Inc. | I2C SPI | 80 MHz | 1.8 V 3.3 V | 1 V | 2 Mbit | 85 °C | -40 °C | 160 kB | Fixed Point | ||||
Cirrus Logic Inc. | I2C SPI | 80 MHz | 1.8 V 3.3 V | 24-VFQFN Exposed Pad | 1 V | 2 Mbit | 24-QFN | 70 °C | 0 °C | 160 kB | Surface Mount | Fixed Point | |
 Cirrus Logic Inc. | I2C SPI | 130 MHz | 1.8 V 3.3 V | 2 Mbit | 20-WLP | 70 °C | 0 °C | 160 kB | Surface Mount | Fixed Point | 1.2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 20.22 | |
| 10 | $ 16.50 | |||
| Tape & Reel (TR) | 6000 | $ 16.50 | ||
Description
General part information
CS48L10 Series
Up to 120-MHz single-core Cirrus Logic 32-bit DSPAdvanced Harvard architecture with separate X, Y, and P memory spaceFixed-point DSP core can perform 2 multiply-and accumulate (MAC) operations (32 x 32) per clock cycleEight 72-bit accumulators20 K words of 32-bit X-data RAM24 K words of 32-bit Y-data RAM20 K words of 32-bit P-code RAM40 K x 32 total ROM
Advanced Harvard architecture with separate X, Y, and P memory space
Fixed-point DSP core can perform 2 multiply-and accumulate (MAC) operations (32 x 32) per clock cycle
Documents
Technical documentation and resources