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NFBGA (NZA)
Integrated Circuits (ICs)

SCANSTA111SM

NRND
Texas Instruments

ENHANCED SCAN BRIDGE MULTIDROP ADDRESSABLE IEEE 1149.1 (JTAG) PORT

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NFBGA (NZA)
Integrated Circuits (ICs)

SCANSTA111SM

NRND
Texas Instruments

ENHANCED SCAN BRIDGE MULTIDROP ADDRESSABLE IEEE 1149.1 (JTAG) PORT

Technical Specifications

Parameters and characteristics for this part

SpecificationSCANSTA111SM
ApplicationsTesting Equipment
InterfaceIEEE 1149.1
Mounting TypeSurface Mount
Package / Case49-LFBGA
Supplier Device Package49-NFBGA (7x7)
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 416$ 11.99
Texas InstrumentsJEDEC TRAY (10+1) 1$ 15.33
100$ 12.50
250$ 9.82
1000$ 8.33

Description

General part information

SCANSTA111 Series

The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.